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crcgen.git
flexiblesizes
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Generator for CRC HDL code (VHDL, Verilog, MyHDL)
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flexiblesizes
generator test: Add support for data sizes != 8
Michael Buesch
3 years
master
Bump version
Michael Buesch
7 months
vhdl
generator: Add VHDL support
Michael Buesch
3 years
Tag
Download
Author
Age
crcgen-2.6
crcgen-2.6.tar.xz
crcgen-2.6.zip
Michael Buesch
7 months
crcgen-2.5
crcgen-2.5.tar.xz
crcgen-2.5.zip
Michael Buesch
13 months
crcgen-2.4
crcgen-2.4.tar.xz
crcgen-2.4.zip
Michael Buesch
18 months
crcgen-2.3
crcgen-2.3.tar.xz
crcgen-2.3.zip
Michael Buesch
18 months
crcgen-2.2
crcgen-2.2.tar.xz
crcgen-2.2.zip
Michael Buesch
3 years
crcgen-2.1
crcgen-2.1.tar.xz
crcgen-2.1.zip
Michael Buesch
3 years
crcgen-2.0
crcgen-2.0.tar.xz
crcgen-2.0.zip
Michael Buesch
3 years
crcgen-1.1
crcgen-1.1.tar.xz
crcgen-1.1.zip
Michael Buesch
4 years
crcgen-1.0
crcgen-1.0.tar.xz
crcgen-1.0.zip
Michael Buesch
5 years
Age
Commit message
Author
Files
Lines
2022-11-26
Move polynomial parser to utils
crcgen-2.4
Michael Buesch
4
-64
/
+68
2022-11-26
tests: Add more polynomial tests
Michael Buesch
1
-0
/
+9
2022-11-26
Stricter polynomial parsing
Michael Buesch
1
-2
/
+4
2022-11-25
Fix typo
Michael Buesch
1
-1
/
+1
2022-11-25
Bump version
Michael Buesch
1
-1
/
+1
2022-11-25
main: Cleanup
Michael Buesch
1
-4
/
+6
2022-11-25
Fix polynomial coefficient conversion for small bit size
Michael Buesch
2
-34
/
+32
2022-11-12
setup: Update description
Michael Buesch
1
-1
/
+1
2022-11-12
Add generator test
crcgen-2.3
Michael Buesch
1
-0
/
+106
2022-11-12
Bump version
Michael Buesch
1
-2
/
+2
[...]
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