crcgen.git - Generator for CRC HDL code (VHDL, Verilog, MyHDL)

Branch	Commit message	Author	Age
flexiblesizes	generator test: Add support for data sizes != 8	Michael Buesch	3 years
master	Bump version	Michael Buesch	7 months
vhdl	generator: Add VHDL support	Michael Buesch	3 years

Tag	Download	Author	Age
crcgen-2.6	crcgen-2.6.tar.xz crcgen-2.6.zip	Michael Buesch	7 months
crcgen-2.5	crcgen-2.5.tar.xz crcgen-2.5.zip	Michael Buesch	13 months
crcgen-2.4	crcgen-2.4.tar.xz crcgen-2.4.zip	Michael Buesch	18 months
crcgen-2.3	crcgen-2.3.tar.xz crcgen-2.3.zip	Michael Buesch	18 months
crcgen-2.2	crcgen-2.2.tar.xz crcgen-2.2.zip	Michael Buesch	3 years
crcgen-2.1	crcgen-2.1.tar.xz crcgen-2.1.zip	Michael Buesch	3 years
crcgen-2.0	crcgen-2.0.tar.xz crcgen-2.0.zip	Michael Buesch	3 years
crcgen-1.1	crcgen-1.1.tar.xz crcgen-1.1.zip	Michael Buesch	4 years
crcgen-1.0	crcgen-1.0.tar.xz crcgen-1.0.zip	Michael Buesch	5 years

Age	Commit message	Author	Files	Lines
2022-11-12	Add generator testcrcgen-2.3	Michael Buesch	1	-0/+106
2022-11-12	Bump version	Michael Buesch	1	-2/+2
2022-11-12	Keep local ref to P	Michael Buesch	1	-1/+2
2022-11-12	Move test code to own file and don't import in normal runs	Michael Buesch	3	-119/+48
2022-11-12	Argument cleanups	Michael Buesch	1	-19/+38
2022-11-12	Hide test mode	Michael Buesch	1	-2/+2
2022-11-12	Update release script	Michael Buesch	1	-2/+1
2022-11-12	Use setuptools instead of distutils	Michael Buesch	1	-1/+1
2022-11-12	Readme: Update name spelling	Michael Buesch	1	-1/+1
2022-11-12	Readme: Add HDL code license	Michael Buesch	1	-2/+19
[...]

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https://git.bues.ch/git/crcgen.git