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crcgen.git
flexiblesizes
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Generator for CRC HDL code (VHDL, Verilog, MyHDL)
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flexiblesizes
generator test: Add support for data sizes != 8
Michael Buesch
3 years
master
Bump version
Michael Buesch
7 months
vhdl
generator: Add VHDL support
Michael Buesch
3 years
Tag
Download
Author
Age
crcgen-2.6
crcgen-2.6.tar.xz
crcgen-2.6.zip
Michael Buesch
7 months
crcgen-2.5
crcgen-2.5.tar.xz
crcgen-2.5.zip
Michael Buesch
13 months
crcgen-2.4
crcgen-2.4.tar.xz
crcgen-2.4.zip
Michael Buesch
18 months
crcgen-2.3
crcgen-2.3.tar.xz
crcgen-2.3.zip
Michael Buesch
18 months
crcgen-2.2
crcgen-2.2.tar.xz
crcgen-2.2.zip
Michael Buesch
3 years
crcgen-2.1
crcgen-2.1.tar.xz
crcgen-2.1.zip
Michael Buesch
3 years
crcgen-2.0
crcgen-2.0.tar.xz
crcgen-2.0.zip
Michael Buesch
3 years
crcgen-1.1
crcgen-1.1.tar.xz
crcgen-1.1.zip
Michael Buesch
4 years
crcgen-1.0
crcgen-1.0.tar.xz
crcgen-1.0.zip
Michael Buesch
5 years
Age
Commit message
Author
Files
Lines
2021-07-13
Update release script
crcgen-2.0
Michael Buesch
1
-1
/
+1
2021-07-13
Bump version
Michael Buesch
1
-3
/
+3
2021-07-12
Add link to generated header
Michael Buesch
1
-0
/
+1
2021-07-12
crcgen/ref: Remove unnecessary shebang
Michael Buesch
1
-1
/
+0
2021-07-11
generator test: Add support for data sizes != 8
flexiblesizes
Michael Buesch
2
-38
/
+66
2021-07-11
generator: Show data width in header
Michael Buesch
1
-2
/
+4
2021-07-11
generator: Swap check for better performance
Michael Buesch
1
-6
/
+6
2021-07-11
generator: Simplify flattening optimizer
Michael Buesch
1
-9
/
+7
2021-07-11
generator: Runtime optimize the XOR optimizer
Michael Buesch
1
-26
/
+18
2021-07-10
generator: Lift crc and data size restrictions
Michael Buesch
4
-96
/
+111
[...]
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