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crcgen.git
flexiblesizes
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Generator for CRC HDL code (VHDL, Verilog, MyHDL)
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Author
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flexiblesizes
generator test: Add support for data sizes != 8
Michael Buesch
3 years
master
Bump version
Michael Buesch
7 months
vhdl
generator: Add VHDL support
Michael Buesch
3 years
Tag
Download
Author
Age
crcgen-2.6
crcgen-2.6.tar.xz
crcgen-2.6.zip
Michael Buesch
7 months
crcgen-2.5
crcgen-2.5.tar.xz
crcgen-2.5.zip
Michael Buesch
13 months
crcgen-2.4
crcgen-2.4.tar.xz
crcgen-2.4.zip
Michael Buesch
18 months
crcgen-2.3
crcgen-2.3.tar.xz
crcgen-2.3.zip
Michael Buesch
18 months
crcgen-2.2
crcgen-2.2.tar.xz
crcgen-2.2.zip
Michael Buesch
3 years
crcgen-2.1
crcgen-2.1.tar.xz
crcgen-2.1.zip
Michael Buesch
3 years
crcgen-2.0
crcgen-2.0.tar.xz
crcgen-2.0.zip
Michael Buesch
3 years
crcgen-1.1
crcgen-1.1.tar.xz
crcgen-1.1.zip
Michael Buesch
4 years
crcgen-1.0
crcgen-1.0.tar.xz
crcgen-1.0.zip
Michael Buesch
5 years
Age
Commit message
Author
Files
Lines
2020-05-19
Bump version
crcgen-1.1
Michael Buesch
1
-1
/
+1
2020-05-19
Fix crash for one optimization combination
Michael Buesch
2
-6
/
+6
2019-08-14
main: Remove unnecessary call to main()
Michael Buesch
3
-10
/
+10
2019-08-13
Change default algorithm to CRC-32
crcgen-1.0
Michael Buesch
1
-1
/
+1
2019-08-13
Update .gitignore
Michael Buesch
1
-0
/
+2
2019-08-13
Add crcgen main script
Michael Buesch
4
-117
/
+178
2019-08-13
Add build framework
Michael Buesch
5
-0
/
+139
2019-08-13
test: Add 64bit coefficients
Michael Buesch
1
-0
/
+6
2019-08-13
test: Add status print
Michael Buesch
1
-0
/
+1
2019-08-13
Move modules to package
Michael Buesch
8
-205
/
+301
[...]
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