blob: aa89f3d10cf00655f33e8ab99697dd7abe7bc9a4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
|
ORGANIZATION_BLOCK OB 1
BEGIN
// Test SFC 47: WAIT
// Zero delay should not wait.
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 0
)
CALL SFC 47 (
WT := 0
)
__ASSERT== __STW BIE, 1
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 4
)
L MD 4
L MD 0
-D
UD DW#16#7FFFFFFF
__ASSERT<= __ACCU 1, 10
// Check short delay.
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 0
)
CALL SFC 47 (
WT := 1
)
__ASSERT== __STW BIE, 1
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 4
)
L MD 4
L MD 0
-D
UD DW#16#7FFFFFFF
__ASSERT<= __ACCU 1, 20
// Check maximum delay.
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 0
)
CALL SFC 47 (
WT := 32767
)
__ASSERT== __STW BIE, 1
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 4
)
L MD 4
L MD 0
-D
UD DW#16#7FFFFFFF
__ASSERT>= __ACCU 1, 32
__ASSERT<= __ACCU 1, 50
// Negative delay should not wait.
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 0
)
CALL SFC 47 (
WT := -1
)
__ASSERT== __STW BIE, 1
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 4
)
L MD 4
L MD 0
-D
UD DW#16#7FFFFFFF
__ASSERT<= __ACCU 1, 10
// Negative delay should not wait.
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 0
)
CALL SFC 47 (
WT := -32768
)
__ASSERT== __STW BIE, 1
CALL SFC 64 ( // Get timestamp
RET_VAL := MD 4
)
L MD 4
L MD 0
-D
UD DW#16#7FFFFFFF
__ASSERT<= __ACCU 1, 10
CALL SFC 46 // STOP CPU
END_ORGANIZATION_BLOCK
|
